Method for measuring effective gate channel length during C-V method

ABSTRACT

The present invention provides a C-V method for measuring an effective channel length in a device, which can simultaneously measure a gate-to-drain overlap length and a gate etch bias length in the device. In the present method, the measured length of the gate by using the present method has a deviation below 5% to compare with the real gate length form SEM. Furthermore, the calculating method of the present invention is only using simple simultaneous equations, which can be measured by a man or a mechanism. As the layout rule shrunk, the present method provides a simple way to measure those parameters, which become more and more important in the device.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to a method for measuring an effective gate channel length, and more particularly relates to a method for measuring an effective channel length during capacitance-voltage (C-V) method.

[0003] 2. Description of the Prior Art

[0004] Channel length is a key parameter in CMOS technology used for performance projection (circuit models), short-channel design, and process monitoring. It usually differs from the gate length by an amount depending on the gate lithography and the etch bias, as well as on the lateral source/drain diffusion.

[0005] In general, channel length is determined by using an I-V (current-voltage) method, which is determined from a series of linear (low-drain-bias) I-V curves of devices with different mask lengths. The channel lengths of MOSFET are becoming increasingly difficult to measure in the deep sub-micron region due to strong variation of mobility with gate voltage, more pronounced effects of graded source/drain doping profiles, and linewidth-dependent lithography bias near the optical resolution limit.

[0006] However, the general I-V method is derived for long-channel devices and is not strictly valid for short-channel devices, so an improved channel-length extraction algorithm, called the shift-and-ratio (S&R) method, is formed. The S&R method is complicated and can not calculate the length of the gate etch bias (L_(pb)) and the length of the gate to drain overlap (L_(overlap)).

[0007] Accordingly, it is obvious that the conventional method for measuring the channel length is defective and then an easy and mendable method is instantly required, especially in the scaling down devices for measuring an effective gate channel length, a gate etch bias length, and a gate to drain overlap length.

SUMMARY OF THE INVENTION

[0008] An object of the invention is using a C-V method to measure an effective gate channel length in a device.

[0009] Another object of the invention is using a C-V method more accurately to measure a gate-to-drain overlap length and a gate etch bias length in a device.

[0010] In order to achieve previous objects of the invention, a method comprises following essential steps. First, a first device is provided with a source/drain and a gate mounted on a substrate. The gate of the first device is in a predetermined length L₁, a predetermined width W₁, and a predetermined height H₁, wherein the predetermined width being orthogonal to the predetermined length of the gate. Next, a negative fixed voltage is applied to the gate of the first device and then a first capacitance between the gate and the source/drain of the first device is measured at the negative fixed voltage. Following, a positive fixed voltage is applied to the gate of the first device and then a second capacitance between the gate and the source/drain of the first device is measured at the positive fixed voltage. Then, a gate-to-drain overlap length of the first device is determined by using the measured first capacitance. Next, a gate etch bias length of the first device is determined by using the measured second capacitance. Last, the effective channel length is calculated from the gate-to-drain overlap length and the gate etch bias length.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The foregoing aspects and many of the accompanying advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

[0012]FIG. 1 is the schematic diagram showing the definition and relationship among various notions of length in a MOS device;

[0013]FIG. 2 is the schematic diagram showing the different predetermined dimension of the gate of the first device, the second device, and the third device;

[0014]FIG. 3 is the schematic diagram showing the split C-V measurement setup;

[0015]FIG. 4 is the schematic diagram showing the measured capacitance from gate to source/drain versus a voltage to a gate for a MOS device; and

[0016]FIG. 5 is the schematic diagram showing the measured capacitance per unit width from gate to source/drain versus a voltage to a gate for a MOS device.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0017] The semiconductor devices of the present invention are applicable to a broad rang of semiconductor devices and can be fabricated from a variety of semiconductor materials. The following description discusses several presently preferred embodiments of the semiconductor devices of the present invention as implemented in silicon substrates, since the majority of currently available semiconductor devices are fabricated in silicon substrates and the most commonly encountered applications of the present invention will involve silicon substrates. Nevertheless, the present invention may also be advantageously employed in gallium arsenide, germanium, and other semiconductor materials. Accordingly, application of the present invention is not intended to be limited to those devices fabricated in silicon semiconductor materials, but will include those devices fabricated in one or more of the available semiconductor materials.

[0018] Further, although the embodiments illustrated herein are show in two-dimensional views with various regions having width and depth, it should be clearly understood that these regions are illustrations of only a portion of a single cell of a device, which may include a plurality of such cells arranged in a three-dimensional structure. Accordingly, these regions will have three dimensions, including length, width and depth, when fabricated in an actual device.

[0019] Referring to FIG. 1, it shows schematically how various notions of length in a MOS device are defined. L_(mask) 62 is a design length on a gate etch mask 60 and it is reproduced on a substrate 10 as L_(gate) 42 of a gate 40 through lithography and etching processes. Depending on the lithography and etching biases, L_(gate) 42 can be either longer or shorter than L_(mask) 62 and L_(pb) is defined as a length of gate etch bias, wherein the length 52 is half gate etch bias length (L_(pb)/2). Although L_(gate) 42 is an important parameter for process control and monitoring, there is no simple way of making a large number of measurements of it. Usually, L_(gate) 42 is measured with a scanning electron microscope (SEM) and only sporadically across the wafer. With the trend of scaling down, a gate-to drain overlap length L_(overlap) 16 becomes more and more important to affect the operation and performance of a MOS device and L_(overlap) is depending on the extension of a source/drain 12 in the substrate 10. L_(eff) is defined as an effective gate channel length between the junction of the source/drain 12 and the parameter L_(eff) 14 must be measured by some electrical characteristics of a MOS device. L_(gate) and L_(eff) can be expressed as an equation (1) and an equation (2)

L _(pb) =L _(mask) −L _(gate)  (1)

L _(eff) =L _(mask) −L _(pb)−2*L _(overlap)  (2)

[0020] where L_(pb) is the length of gate etch bias, L_(mask) is the design length on a gate etch mask, L_(gate) is the length of the gate, and L_(overlap) is the length of gate-to-drain overlap.

[0021] The method of the present invention comprises following steps. First, a first device, a second device, and a third device are provided and each one of those devices is with a source/drain and a gate mounted on a substrate, as shown in FIG. 1. Referring to FIG. 2, it is the schematic diagram showing the different predetermined dimension of the gate of those devices. The predetermined length, the predetermined width, and the predetermined height of gates 201, 202, and 203 of the first device, the second device, and the third device L₁, W₁, H₁; L₂, W₂, H₂; and L₃, W₃, H₃ are L, W, H; L/2, W, H; and L, W/2, H. The first device and the second are different only on the width of the gate. The first device and the third device are different only on the length of the gate. Those devices have an intrinsic capacitance per unit width C_(total) between the gate and the source/drain at a fixed voltage to the gate, wherein C_(total) can be expressed as an equation (3)

C _(total) =C _(gate)+2*C _(overlap)+2*C _(fringing)+(C _(offset) /W)  (3)

[0022] where C_(total) is the intrinsic capacitance per unit width between the gate and the source/drain, C_(gate) is an intrinsic gate-to-channel captacitance per unit width, C_(overlap) is a gate-to-drain overlap captacitance per unit width, C_(fringing) is a fringing captacitance per unit width, C_(offset) is a deviation captacitance from a measuring apparatus, and W is the predetermined width of the gate. Furthermore, the fringing captacitance per unit width C_(fringing) can be expressed as an equation (4)

C _(fringing)=2*ε_(oxide) /π*ln[1+(H _(gate) /H _(gate oxide))]  (4)

[0023] where H_(gate) is the predetermined high of the gate, H_(gate oxide) is the height of the gate oxide layer 20 as shown in FIG. 1, and ε_(oxide) is the field of the gate oxide layer. In the present method, H_(gate), H_(gate oxide)) and ε_(oxide) are constants, so C_(fringing) is also a constant.

[0024] Next, an electrical signals testing is performed to acquire some characteristics of those devices to measure the effective channel gate length. The electrical testing, which is shown in FIG. 4, is performed in a C-V setup as shown in FIG. 3. As the intrinsic capacitance per unit width C_(total) at a negative fixed voltage to the gate, C_(total) can be expressed as an accumulation capacitance per unit width C_(accumulation), which is expressed as an equation (5)

C _(accumulation)=2*C _(overlap)+2*C _(fringing)+(C _(offset) /W)  (5)

[0025] where C_(accumulation) is an accumulation capacitance per unit width at a negative fixed voltage to the gate. Referring FIG. 5, the gate-to-drain overlap captacitance per unit width C_(overlap) has very little difference at the accumulation region.

[0026] In another condition, when the intrinsic capacitance per unit width C_(total) is at a positive fixed voltage to the gate, C_(total) can be expressed as an inversion capacitance per unit width C_(inversion), which is expressed as an equation (6)

C _(inversion) =C _(gate)+2*C _(fringing)+(C _(offset) /W)  (6)

[0027] where C_(inversion) is an inversion capacitance per unit width at a positive fixed voltage to the gate.

[0028] Following, measuring the effective channel gate length comprises following steps. First, a negative fixed voltage is applied to the gate of the first device and the second device. Then, a first capacitance between the gate and the source/drain of the first device C_(acculumation,measured,1) and a second capacitance between the gate and the source/drain of the second device C_(acculumation,measured,2) are measured at the negative fixed voltage. Next, C_(acculumation,measured,1) and C_(acculumation,measured,2) are put in the equation (5) to become an equation (5-1) and an equation (5-2)

C _(accumulatlon,measured,1)=2*C _(overlap,1) *W ₁+2*C _(fringing,1) *W ₁ +C _(offset,1)  (5-1)

C _(accumulation,measured,2)=2*C _(overlap,2) *W ₂+2*C _(fringing,2) *W ₂ +C _(offset,2)  (5-2)

[0029] where W₁ and W₂ are known; and C_(fringing,1) and C_(fringing,2) are constant. Because C_(overlap) has a very small difference at accumulation region, so C_(overlap,1) and C_(overlap,2) can be meant equal. However, because C_(offset) is produced from the measuring apparatus, so C_(offset) is a constant. Thus, solving the equation (5-1) and the equation (5-2) can acquire C_(overlap) and C_(offset).

[0030] Furthermore, the gate-to-drain overlap length L_(overlap) of the first device can be calculated according to an equation (7)

L _(overlap)=(H _(gate oxide) *C _(overlap))/ε_(oxide)  (7)

[0031] where H_(gate oxide) is the height of the gate oxide layer 20 as shown in FIG. 1, and ε_(oxide) is the field of the gate oxide layer.

[0032] Next, a positive fixed voltage is applied to the gate of the first device and the third device. Then, a third capacitance between the gate and the source/drain of the first device C_(inversion,measured,1) and a foruth capacitance between the gate and the source/drain of the second device C_(inversion,measured,3) are measured at the negative fixed voltage. Next, C_(inversion,measured,1) and C_(inversion,measured,3) are put in the equation (6) to become an equation (6-1) and an equation (6-2)

C _(inversion,measured,1=) C _(gate,1) *W ₁+2*C _(fringing,1) *W ₁ +C _(offset,1)  (6-1)

C _(inversion,measured,3) =C _(gate,3) *W ₃+2*C _(fringing,3) *W ₃ +C _(offset,3)  (6-2)

[0033] where W₁ and W₃ are known and equal; and C_(fringing,1) and C_(fringing,3) are constant. Thus, C_(gate,1) and C_(gate,1) can be acquired from the equation (6-1) and the equation (6-2). Furthermore, the length of the gate of the first device L_(gate) can be acquired from an equation (8)

L _(gate)=(C _(gate) *W)*(L ₁ −L ₃)/[(C _(gate,1) −C _(gate,3))*W]  (8)

[0034] where L_(gate) is the length of the gate of the first device; C_(gate) is equal to C_(gate,1); and W is equal to W₁ and W₃.

[0035] Following step, the gate etch bias length L_(pb) can be calculated by the equation (1), where L_(pb)=L_(mask)−L_(gate). Finally, the effective channel length L_(eff) of the first device can be calculated by the equation (2), where

L _(eff) =L _(mask) −L _(pb)−2*L _(overlap).

[0036] To sum up the foregoing, the present invention provides a C-V method for measuring an effective channel length in a device, which can simultaneously measure a gate-to-drain overlap length and a gate etch bias length in the device. In the present method, the measured length of the gate by using the present method has a deviation below 5% to compare with the real gate length form SEM. Furthermore, the calculating method of the present invention is only using simple simultaneous equations, which can be measured by a man or a mechanism. As the layout rule shrunk, the present invention provides a simple way to measure those parameters, which become more and more important in the device.

[0037] Of course, it is to be understood that the invention need not be limited to these disclosed embodiments. Various modification and similar changes are still possible within the spirit of this invention. In this way, the scope of this invention should be defined by the appended claims. 

What is claimed is:
 1. A method for measuring an effective gate channel length during a capacitance-voltage (C-V) method, said method comprising: providing a first device with a source/drain and a gate mounted on a substrate, wherein said gate being in a predetermined length L₁, a predetermined width W₁, and a predetermined height H₁, and said predetermined width being orthogonal to said predetermined length of said gate; applying a negative fixed voltage to said gate of said first device; measuring a first capacitance between said gate and said source/drain of said first device at said negative fixed voltage; applying a positive fixed voltage to said gate of said first device; measuring a second capacitance between said gate and said source/drain of said first device at said positive fixed voltage; using said measured first capacitance to determine a gate-to-drain overlap length of said first device; using said measured second capacitance to determine a gate etch bias length of said first device; and calculating said effective channel length from said gate-to-drain overlap length and said gate etch bias length.
 2. The method according to claim 1, wherein said first device has an intrinsic capacitance per unit width C_(total) between said gate and said source/drain, and wherein said C_(total) can be shown according to a first equation C _(total) =C _(gate)+2*C _(overlap)+2*C _(fringing)+(C _(offset) /W)where C_(gate is an intrinsic gate-to-channel captacitance per unit width,) C_(overlap) is a gate-to-drain overlap captacitance per unit width, C_(fringing) is a fringing captacitance per unit width, C_(offset) is a deviation captacitance from a measuring apparatus, and W is said predetermined width of said gate.
 3. The method according to claim 2, wherein said intrinsic capacitance per unit width C_(total) at said negative fixed voltage can be expressed as an accumulation capacitance per unit width C_(accumulation) which is according to a second equation C _(accumulation)=2*C _(overlap)+2*C _(fringing)+(C _(offset) /W)
 4. The method according to claim 3, wherein said step of using said measured first capacitance to determine said gate-to-drain overlap length of said first device, comprises following steps: putting said measured first capacitance C_(accumulation,measured,1) into said second equation to become a third equation C _(accumulation,measured,1)2*C _(overlap,1)+2*C _(fringing,1) *W ₁ +C _(offset,1) providing a second device with a gate only having a different predetermined width W₂ to said first device; applying said negative fixed voltage to a gate of said second device; measuring a third capacitance between said gate and said source/drain of said second device at said negative fixed voltage; putting said measured third capacitance C_(accumulation,measured,2) into said second equation to become a fourth equation C _(accumulation,measured,2)=2*C _(overlap,2) *W ₂+2*C _(fringing,2) *W ₂ +C _(offset,2) using said third equation and said fourth equation to calculate said gate-to-drain overlap capacitance per unit width C_(overlap) of said first device.
 5. The method according to claim 4, wherein said gate-to-drain overlap length L_(overlap) of said first device is calculated according to a fifth equation L _(overlap)=(H _(gate oxide) *C _(overlap))/ ε_(oxide) where H_(gate oxide) is a height of a gate oxide layer of said first device and ε_(oxide) is a field of said gate oxide of said first device.
 6. The method according to claim 2, wherein said intrinsic capacitance per unit width C_(total) at said positive fixed voltage can be expressed as an inversion capacitance per unit width C_(inversion) which is according to a sixth equation C _(inversion) =C _(gate)+2*C _(fringing)+(C _(offset) /W)
 7. The method according to claim 6, wherein said step of using said measured second capacitance to determine said gate etch bias length of said first device, comprises following steps: putting said measured second capacitance C_(inversion,measured,1) into said sixth equation to become a seventh equation C _(inversion,measured,1) C _(gate,1) *W ₁+2*C _(fringing,1) *W ₁ +C _(offset,1) providing a third device with a gate only having a different predetermined length L₃ to said first device; applying said positive fixed voltage to a gate of said third device; measuring a fourth capacitance between said gate and said source/drain of said third device at said positive fixed voltage; putting said measured fourth capacitance C_(inversion,measured,3) into said fifth equation to become an eighth equation C _(inversion,measured,3) =C _(gate,3) W ₃+2*C _(fringing,3) W ₃ +C _(offset,3) where W₃ is a predetermined width of said gate of said third device and W₃ is equal to W₁; and using said seventh equation and said eighth equation to calculate an effective gate length L_(gate) of said first device.
 8. The method according to claim 7, wherein said gate etch bias length L_(pb) is calculated by a ninth equation L _(pb) =L _(mask) −L _(gate) where L_(mask) is a length of a mask for defining said predetermined length of said gate of first device and L_(gate) is said effective gate channel length of said first device.
 9. The method according to claim 8, wherein said effective gate channel length L_(eff) of said first device is calculated by a tenth equation L _(eff) =L _(mask) −L _(pb)−2*L _(overlap)
 10. A method for measuring an effective channel length during a capacitance-voltage (C-V) method, said method comprising: providing a first device with a source/drain and a gate mounted on a substrate, wherein said gate being in a predetermined length L₁, a predetermined width W₁, and a predetermined height H₁, and said predetermined width being orthogonal to said predetermined length of said gate, and wherein said first device has an intrinsic capacitance per unit width C_(total) between said gate and said source/drain, and said C_(total) can be shown according to a first equation C _(total) =C _(gate)+2*C _(overlap)+2*C _(fringing)+(C _(offset) /W) where C_(gate) is an intrinsic gate-to-channel captacitance per unit width, C_(overlap) is a gate-to-drain overlap captacitance per unit width, C_(fringing) is a fringing captacitance per unit width, C_(offset) is a deviation captacitance from a measuring apparatus, and W is said predetermined width of said gate; applying a negative fixed voltage to said gate of said first device, wherein said intrinsic capacitance per unit width C_(total) at said negative fixed voltage being expressed as an accumulation capacitance per unit width C_(accumulation) which is according to a second equation C _(accumulation)=2*C _(overlap) +2*C _(fringing)+(C _(offset) /W); measuring a first capacitance between said gate and said source/drain of said first device at said negative fixed voltage; applying a positive fixed voltage to said gate of said first device, wherein said intrinsic capacitance per unit width C_(total) at said positive fixed voltage being expressed as an inversion capacitance per unit width C_(inversion) which is according to a third equation C _(inversion) =C _(gate)+2*C _(fringing)+(C _(offset) /W); measuring a second capacitance between said gate and said source/drain of said first device at said positive fixed voltage; using said measured first capacitance to determine a gate-to-drain overlap length of said first device; using said measured second capacitance to determine a gate etch bias length of said first device; and calculating said effective channel length from said gate-to-drain overlap length and said gate etch bias length.
 11. The method according to claim 10, wherein said step of using said measured first capacitance to determine said gate-to-drain overlap length of said first device, comprises following steps: putting said measured first capacitance C_(accumulation,measured,1) into said second equation to become a fourth equation C _(accumulation,measured,1)=2*C _(overlap,1) *W ₁+2*C _(fringing,1) *W ₁ +C _(offset,1) providing a second device with a gate only having a different predetermined width W₂ to said first device; applying said negative fixed voltage to a gate of said second device; measuring a third capacitance between said gate and said source/drain of said second device at said negative fixed voltage; putting said measured third capacitance C_(accumulation,measured,2) into said second equation to become an equation fifth C _(accumulation,measured,2)=2*C _(overlap,2) *W ₂+2*C _(fringing,2) *W ₂ +C _(offset,2) using said fourth equation and said fifth equation to calculate said gate-to-drain overlap capacitance per unit width C_(overlap) of said first device.
 12. The method according to claim 11, wherein said gate-to-drain overlap length L_(overlap) of said first device is calculated according to a sixth equation L _(overlap)=(H _(gate oxide) *C _(overlap))/ε_(oxide) where H_(gate oxide) is a height of a gate oxide layer of said first device and ε_(oxide) is a field of said gate oxide of said first device.
 13. The method according to claim 10, wherein said step of using said measured second capacitance to determine said gate etch bias length of said first device, comprises following steps: putting said measured second capacitance C_(inversion,measured,1) into said third equation to become a seventh equation C _(inversion,measured,1) =C _(gate,1) *W ₁+2*C _(fringing,1) +C _(offset,1) providing a third device with a gate only having a different predetermined length L₃ to said first device; applying said positive fixed voltage to a gate of said third device; measuring a fourth capacitance between said gate and said source/drain of said third device at said positive fixed voltage; putting said measured fourth capacitance C_(inversion,measured,3) into said third equation to become an eighth equation C _(inversion,measured,3) =C _(gate,3) *W ₃+2*C _(fringing,3) *W ₃ +C _(offset,3) where W₃ is a predetermined width of said gate of said third device and W₃ is equal to W₁; and using said seventh equation and said eighth equation to calculate an effective gate length L_(gate) of said first device.
 14. The method according to claim 13, wherein said gate etch bias length L_(pb) is calculated by a ninth equation L _(pb) =L _(mask) −L _(gate) where L_(mask) is a length of a mask for defining said predetermined length of said gate of first device and L_(gate) is said effective gate channel length of said first device.
 15. The method according to claim 14, wherein said effective gate channel length L_(eff) of said first device is calculated by a tenth equation L _(eff) =L _(mask) −L _(pb)−2*L _(overlap) 